/******************************************************************************
 ** File Name:      pmu.c                                                     *
 ** Author:         Sky.Li
 ** DATE:           12/02/2019                                                *
 ** Copyright:      2019 Spreatrum, Incoporated. All Rights Reserved.         *
 ** Description:    This file defines the basic information on chip.          *
 ******************************************************************************

 ******************************************************************************
 **                        Edit History                                       *
 ** ------------------------------------------------------------------------- *
 ** DATE           NAME             DESCRIPTION                               *
 ** 12/02/2019     Sky.Li	    Create.                                   *
 ******************************************************************************/

/**---------------------------------------------------------------------------*
 **                         Dependencies                                      *
 **---------------------------------------------------------------------------*/
#include <asm/io.h>
#include "adi_hal_internal.h"
//#include "asm/arch/wdg_drvapi.h"
#include "asm/arch-orca/sprd_reg.h"
#include "asm/arch-orca/common.h"
/**---------------------------------------------------------------------------*
 **                         Compiler Flag                                     *
 **---------------------------------------------------------------------------*/
#ifdef   __cplusplus
extern   "C"
{
#endif

#define AON_IDLE_CLK_4M_AON 0x1

void pmu_commom_config(void)
{
	CHIP_REG_SET(REG_PMU_APB_PD_APCPU_TOP_CFG,
		//BIT_PMU_APB_PD_APCPU_TOP_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_APCPU_TOP_PD_SEL |
		//BIT_PMU_APB_PD_APCPU_TOP_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_APCPU_TOP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_APCPU_TOP_PWR_ON_SEQ_DLY(0x2) |
		BIT_PMU_APB_PD_APCPU_TOP_ISO_ON_DLY(0x3) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_APCPU_C0_CFG,
		//BIT_PMU_APB_PD_APCPU_C0_WFI_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_APCPU_C0_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_APCPU_C0_PD_SEL |
		//BIT_PMU_APB_PD_APCPU_C0_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_APCPU_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_APCPU_C0_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_APCPU_C0_PWR_ON_SEQ_DLY(0xA) |
		BIT_PMU_APB_PD_APCPU_C0_ISO_ON_DLY(0x1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_APCPU_C1_CFG,
		//BIT_PMU_APB_PD_APCPU_C1_WFI_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_APCPU_C1_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_APCPU_C1_PD_SEL |
		BIT_PMU_APB_PD_APCPU_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_APCPU_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_APCPU_C1_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_APCPU_C1_PWR_ON_SEQ_DLY(0x9) |
		BIT_PMU_APB_PD_APCPU_C1_ISO_ON_DLY(0x2) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_APCPU_TOP_CFG2,
		BIT_PMU_APB_PD_APCPU_TOP_DCDC_PWR_ON_DLY(0x50) |
		BIT_PMU_APB_PD_APCPU_TOP_DCDC_PWR_OFF_DLY(0x50) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_NRCP_SYS_CFG,
		//BIT_PMU_APB_PD_NRCP_SYS_DBG_SHUTDOWN_EN |
		BIT_PMU_APB_PD_NRCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_NRCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_NRCP_SYS_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_NRCP_SYS_PWR_ON_SEQ_DLY(0x1) |
		BIT_PMU_APB_PD_NRCP_SYS_ISO_ON_DLY(0x6) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
		//BIT_PMU_APB_PD_AP_SYS_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_AP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AP_SYS_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_AP_SYS_PWR_ON_SEQ_DLY(0x1) |
		BIT_PMU_APB_PD_AP_SYS_ISO_ON_DLY(0x1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_NRCP_DL_CFG,
		BIT_PMU_APB_PD_NRCP_DL_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_NRCP_DL_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_NRCP_DL_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_NRCP_DL_PWR_ON_SEQ_DLY(0x2) |
		BIT_PMU_APB_PD_NRCP_DL_ISO_ON_DLY(0x1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_NRCP_UL_CFG,
		BIT_PMU_APB_PD_NRCP_UL_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_NRCP_UL_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_NRCP_UL_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_NRCP_UL_PWR_ON_SEQ_DLY(0x3) |
		BIT_PMU_APB_PD_NRCP_UL_ISO_ON_DLY(0x2) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_NRCP_SYNC_CFG,
		BIT_PMU_APB_PD_NRCP_SYNC_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_NRCP_SYNC_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_NRCP_SYNC_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_NRCP_SYNC_PWR_ON_SEQ_DLY(0x4) |
		BIT_PMU_APB_PD_NRCP_SYNC_ISO_ON_DLY(0x3) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_V3_PS_CFG,
		//BIT_PMU_APB_PD_V3_PS_PD_SEL |
		//BIT_PMU_APB_PD_V3_PS_DBG_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_PS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_V3_PS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_PS_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_V3_PS_PWR_ON_SEQ_DLY(0x2) |
		BIT_PMU_APB_PD_V3_PS_ISO_ON_DLY(0x2) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_V3_LCE_CFG,
		BIT_PMU_APB_PD_V3_LCE_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_V3_LCE_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_LCE_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_V3_LCE_PWR_ON_SEQ_DLY(0x8) |
		BIT_PMU_APB_PD_V3_LCE_ISO_ON_DLY(0x6) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_V3_DPFEC_CFG,
		BIT_PMU_APB_PD_V3_DPFEC_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_V3_DPFEC_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_DPFEC_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_V3_DPFEC_PWR_ON_SEQ_DLY(0x7) |
		BIT_PMU_APB_PD_V3_DPFEC_ISO_ON_DLY(0x5) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_NRCP_DSP_0_CFG,
		//BIT_PMU_APB_PD_NRCP_DSP_0_PD_SEL |
		BIT_PMU_APB_PD_NRCP_DSP_0_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_NRCP_DSP_0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_NRCP_DSP_0_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_NRCP_DSP_0_PWR_ON_SEQ_DLY(0x5) |
		BIT_PMU_APB_PD_NRCP_DSP_0_ISO_ON_DLY(0x4) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_NRCP_DSP_1_CFG,
		//BIT_PMU_APB_PD_NRCP_DSP_1_PD_SEL |
		BIT_PMU_APB_PD_NRCP_DSP_1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_NRCP_DSP_1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_NRCP_DSP_1_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_NRCP_DSP_1_PWR_ON_SEQ_DLY(0x6) |
		BIT_PMU_APB_PD_NRCP_DSP_1_ISO_ON_DLY(0x5) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_V3_WCE_CFG,
		BIT_PMU_APB_PD_V3_WCE_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_V3_WCE_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_WCE_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_V3_WCE_PWR_ON_SEQ_DLY(0x6) |
		BIT_PMU_APB_PD_V3_WCE_ISO_ON_DLY(0x4) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_V3_PHY_CFG,
		//BIT_PMU_APB_PD_V3_PHY_PD_SEL |
		//BIT_PMU_APB_PD_V3_PHY_DBG_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_PHY_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_V3_PHY_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_PHY_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_V3_PHY_PWR_ON_SEQ_DLY(0x3) |
		BIT_PMU_APB_PD_V3_PHY_ISO_ON_DLY(0x8) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_V3_LWPROC_CFG,
		BIT_PMU_APB_PD_V3_LWPROC_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_V3_LWPROC_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_LWPROC_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_V3_LWPROC_PWR_ON_SEQ_DLY(0x5) |
		BIT_PMU_APB_PD_V3_LWPROC_ISO_ON_DLY(0x7) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_V3_TD_CFG,
		BIT_PMU_APB_PD_V3_TD_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_V3_TD_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_TD_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_V3_TD_PWR_ON_SEQ_DLY(0x4) |
		BIT_PMU_APB_PD_V3_TD_ISO_ON_DLY(0x3) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_V3_MODEM_SYS_CFG,
		BIT_PMU_APB_PD_V3_MODEM_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_V3_MODEM_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_V3_MODEM_SYS_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_V3_MODEM_SYS_PWR_ON_SEQ_DLY(0x1) |
		BIT_PMU_APB_PD_V3_MODEM_SYS_ISO_ON_DLY(0x9) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_PSCP_SYS_CFG,
		//BIT_PMU_APB_PD_PSCP_SYS_DBG_SHUTDOWN_EN |
		BIT_PMU_APB_PD_PSCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_PSCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_PSCP_SYS_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_PSCP_SYS_PWR_ON_SEQ_DLY(0x1) |
		BIT_PMU_APB_PD_PSCP_SYS_ISO_ON_DLY(0x1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AUDCP_AUDDSP_CFG,
		//BIT_PMU_APB_PD_AUDCP_AUDDSP_PD_SEL |
		BIT_PMU_APB_PD_AUDCP_AUDDSP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AUDCP_AUDDSP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AUDCP_AUDDSP_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_AUDCP_AUDDSP_PWR_ON_SEQ_DLY(0x3) |
		BIT_PMU_APB_PD_AUDCP_AUDDSP_ISO_ON_DLY(0x1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AUDCP_SYS_CFG,
		BIT_PMU_APB_PD_AUDCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AUDCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AUDCP_SYS_PWR_ON_DLY(0x1) |
		BIT_PMU_APB_PD_AUDCP_SYS_PWR_ON_SEQ_DLY(0x1) |
		BIT_PMU_APB_PD_AUDCP_SYS_ISO_ON_DLY(0x3) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
		BIT_PMU_APB_XTLBUF1_WAIT_CNT(0x2) |
		BIT_PMU_APB_XTLBUF0_WAIT_CNT(0x2) |
		BIT_PMU_APB_XTL1_WAIT_CNT(0x46) |
		BIT_PMU_APB_XTL0_WAIT_CNT(0x46) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT0,
		BIT_PMU_APB_PCIEPLL_H_WAIT_CNT(0x7) |
		BIT_PMU_APB_R8PLL_WAIT_CNT(0x7) |
		BIT_PMU_APB_MPLL1_WAIT_CNT(0xF) |
		BIT_PMU_APB_MPLL0_WAIT_CNT(0xF) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
		BIT_PMU_APB_V3PLL_WAIT_CNT(0x7) |
		BIT_PMU_APB_NRPLL_WAIT_CNT(0x7) |
		BIT_PMU_APB_DPLL1_WAIT_CNT(0x7) |
		BIT_PMU_APB_DPLL0_WAIT_CNT(0x7) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
		BIT_PMU_APB_NR_RPLL_WAIT_CNT(0x4) |
		BIT_PMU_APB_V3_RPLL_WAIT_CNT(0x4) |
		BIT_PMU_APB_NR_CPUPLL_WAIT_CNT(0x7) |
		BIT_PMU_APB_NR_DSPPLL_WAIT_CNT(0x7) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_XTLBUF_LDO_WAIT_CNT,
		BIT_PMU_APB_XTLBUF1_LDO_WAIT_CNT(0x1) |
		BIT_PMU_APB_XTLBUF0_LDO_WAIT_CNT(0x1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG0,
		BIT_PMU_APB_AUDCP_PWR_WAIT_CNT(0x8) |
		BIT_PMU_APB_PSCP_PWR_WAIT_CNT(0x8) |
		BIT_PMU_APB_V3_MODEM_PWR_WAIT_CNT(0x8) |
		BIT_PMU_APB_AP_PWR_WAIT_CNT(0x8) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG1,
		BIT_PMU_APB_IPA_PWR_WAIT_CNT(0x8) |
		BIT_PMU_APB_SP_SYS_PWR_WAIT_CNT(0x8) |
		BIT_PMU_APB_NRCP_PWR_WAIT_CNT(0x8) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_RCO_CNT_WAIT_CFG,
		BIT_PMU_APB_RCO_WAIT_CNT(0xB) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PMU_CLK_DIV_CFG,
		BIT_PMU_APB_PWR_ST_CLK_DIV_CFG(0xF) |
		BIT_PMU_APB_SLP_CTRL_CLK_DIV_CFG(0x80) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_CGM_PMU_SEL,
		BIT_PMU_APB_CGM_PMU_SEL_REG(0x2) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_DGB_PARAMETER,
		BIT_PMU_APB_RAM_PWR_DLY(0x2) |
		BIT_PMU_APB_ISO_OFF_DLY(0x1) |
		BIT_PMU_APB_CGM_ON_DLY(0x1) |
		BIT_PMU_APB_RST_ASSERT_DLY(0x1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_ANALOG_PHY_PD_CFG,
		//BIT_PMU_APB_CSI_2P2LANE_PD_REG |
		BIT_PMU_APB_PHY_PWR_DLY(0x1) |
		//BIT_PMU_APB_DSI_PD_REG |
		//BIT_PMU_APB_PCIE2_PD_REG |
		//BIT_PMU_APB_CSI_4LANE1_PD_REG |
		//BIT_PMU_APB_CSI_4LANE0_PD_REG |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PUB_VOL_DOWN_CFG,
		BIT_PMU_APB_PUB_VOL_UP_CNT(0xFF) |
		BIT_PMU_APB_PUB_VOL_DOWN_CNT(0xFF) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT3,
		BIT_PMU_APB_R5PLL_WAIT_CNT(0x7) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_R5PLL_RST_CTRL_CFG,
		//BIT_PMU_APB_R5PLL_RST_CTRL_BYPASS |
		BIT_PMU_APB_R5PLL_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_R5PLL_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_R5PLL_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PCIEPLL_H_RST_CTRL_CFG,
		//BIT_PMU_APB_PCIEPLL_H_RST_CTRL_BYPASS |
		BIT_PMU_APB_PCIEPLL_H_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_PCIEPLL_H_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_PCIEPLL_H_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_APCPU_MODE_ST_CFG,
		BIT_PMU_APB_APCPU_CORINTH_RAM_PWR_DLY(0x1) |
		BIT_PMU_APB_APCPU_CORE_RAM_PWR_DLY(0x1) |
		BIT_PMU_APB_APCPU_CORE_INITIAL_DLY(0xA) |
		BIT_PMU_APB_APCPU_CORINTH_INITIAL_DLY(0xA) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_MPLL_WAIT_CLK_DIV_CFG,
		BIT_PMU_APB_MPLL_WAIT_CLK_DIV_CFG(0x0) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_MPLL0_RST_CTRL_CFG,
		//BIT_PMU_APB_MPLL0_RST_CTRL_BYPASS |
		BIT_PMU_APB_MPLL0_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_MPLL0_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_MPLL0_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_MPLL1_RST_CTRL_CFG,
		//BIT_PMU_APB_MPLL1_RST_CTRL_BYPASS |
		BIT_PMU_APB_MPLL1_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_MPLL1_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_MPLL1_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_R8PLL_RST_CTRL_CFG,
		//BIT_PMU_APB_R8PLL_RST_CTRL_BYPASS |
		BIT_PMU_APB_R8PLL_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_R8PLL_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_R8PLL_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_NR_CPUPLL_RST_CTRL_CFG,
		//BIT_PMU_APB_NR_CPUPLL_RST_CTRL_BYPASS |
		BIT_PMU_APB_NR_CPUPLL_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_NR_CPUPLL_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_NR_CPUPLL_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_DPLL0_RST_CTRL_CFG,
		//BIT_PMU_APB_DPLL0_RST_CTRL_BYPASS |
		BIT_PMU_APB_DPLL0_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_DPLL0_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_DPLL0_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_DPLL1_RST_CTRL_CFG,
		//BIT_PMU_APB_DPLL1_RST_CTRL_BYPASS |
		BIT_PMU_APB_DPLL1_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_DPLL1_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_DPLL1_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_V3PLL_RST_CTRL_CFG,
		//BIT_PMU_APB_V3PLL_RST_CTRL_BYPASS |
		BIT_PMU_APB_V3PLL_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_V3PLL_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_V3PLL_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_NRPLL_RST_CTRL_CFG,
		//BIT_PMU_APB_NRPLL_RST_CTRL_BYPASS |
		BIT_PMU_APB_NRPLL_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_NRPLL_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_NRPLL_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_NR_DSPPLL_RST_CTRL_CFG,
		//BIT_PMU_APB_NR_DSPPLL_RST_CTRL_BYPASS |
		BIT_PMU_APB_NR_DSPPLL_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_NR_DSPPLL_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_NR_DSPPLL_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_V3_RPLL_RST_CTRL_CFG,
		//BIT_PMU_APB_V3_RPLL_RST_CTRL_BYPASS |
		BIT_PMU_APB_V3_RPLL_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_V3_RPLL_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_V3_RPLL_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_NR_RPLL_RST_CTRL_CFG,
		//BIT_PMU_APB_NR_RPLL_RST_CTRL_BYPASS |
		BIT_PMU_APB_NR_RPLL_DELAY_PWR_ON(0x1A) |
		BIT_PMU_APB_NR_RPLL_DELAY_EN_OFF(0x4) |
		BIT_PMU_APB_NR_RPLL_DELAY_RST_ASSERT(0x1A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_APCPU_MODE_ST_CFG1,
		BIT_PMU_APB_APCPU_CORE_RST_DEASSERT_DLY(0x2) |
		BIT_PMU_APB_APCPU_CORE_RST_ASSERT_DLY(0x2) |
		BIT_PMU_APB_APCPU_CORINTH_RST_DEASSERT_DLY(0x2) |
		BIT_PMU_APB_APCPU_CORINTH_RST_ASSERT_DLY(0x2) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_APCPU_MODE_ST_CFG2,
		BIT_PMU_APB_APCPU_CORE_CGM_OFF_DLY(0x2) |
		BIT_PMU_APB_APCPU_CORE_CGM_ON_DLY(0x2) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_SP_CLK_GATE_BYP_CFG,
		BIT_PMU_APB_SP_PWR_PD_AON_MEM_BYP |
		//BIT_PMU_APB_SP_PWR_PD_SP_MEM_BYP |
		0
	);
}

void apcpu_hw_dvfs_config(void)
{
	/* Disable apcpu dvfs upd delay en bit */
	CHIP_REG_AND(REG_APCPU_DVFS_APB_APCPU_FREQ_UPD_TYPE_CFG, ~(
		BIT_APCPU_DVFS_APB_APCPU_GIC_FREQ_UPD_DELAY_EN    |
		BIT_APCPU_DVFS_APB_APCPU_PERIPH_FREQ_UPD_DELAY_EN |
		BIT_APCPU_DVFS_APB_APCPU_ATB_FREQ_UPD_DELAY_EN    |
		BIT_APCPU_DVFS_APB_APCPU_SCU_FREQ_UPD_DELAY_EN    |
		BIT_APCPU_DVFS_APB_APCPU_CORE1_FREQ_UPD_DELAY_EN  |
		BIT_APCPU_DVFS_APB_APCPU_CORE0_FREQ_UPD_DELAY_EN
	));
}

//PMU pad out select config
void pad_out_sel_config(void)
{
	CHIP_REG_SET(REG_PMU_APB_PAD_OUT_XTL_EN0_CFG,
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_CDMA_AUTO_DEEP_SLEEP_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_CDMA_DEEP_SLEEP_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_POL_SEL |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_TOP_DVFS_DEEP_SLEEP_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_PLL_PD_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_EXT_XTL_PD_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_SP_SYS_DEEP_SLEEP_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_AP_DEEP_SLEEP_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_PUB_SYS_DEEP_SLEEP_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_APCPU_C7_PD_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_APCPU_TOP_PD_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_WTLCP_DEEP_SLEEP_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_PUBCP_DEEP_SLEEP_MASK |
		//BIT_PMU_APB_PAD_OUT_XTL_EN0_AUDCP_DEEP_SLEEP_MASK |
		0
	);
}

//AON idle config
void aon_idle_config(void)
{
	//pub sleep condition
	CHIP_REG_OR(REG_PMU_APB_LIGHT_SLEEP_ENABLE, BIT_PMU_APB_AON_LSLP_ENA);
	//Enable aon idle
	CHIP_REG_OR(REG_AON_APB_AON_APB_FREQ_CTRL, BIT_AON_APB_AON_APB_IDLE_EN);
	//4M clock when aon idle
	CHIP_REG_SET(REG_AON_APB_AON_APB_CLK_SEL, AON_IDLE_CLK_4M_AON);
}

//AON lpc config
void aon_lpc_config(void)
{
	CHIP_REG_OR(REG_AON_APB_APCPU_AXI_CTRL,
		BIT_AON_APB_CGM_APCPU_AXI_AUTO_FREQ_DOWN_CTRL_SEL |
		BIT_AON_APB_CGM_APCPU_AXI_AUTO_FREQ_DOWN_EN
	);
	CHIP_REG_OR(REG_AON_APB_APCPU_CLUSTER_ATB_LPC_CTRL, BIT_AON_APB_APCPU_CLUSTER_ATB_LP_EB);
	CHIP_REG_OR(REG_AON_APB_APCPU_CLUSTER_APB_LPC_CTRL, BIT_AON_APB_APCPU_CLUSTER_APB_LP_EB);
	CHIP_REG_OR(REG_AON_APB_APCPU_CLUSTER_GIC_LPC_CTRL, BIT_AON_APB_APCPU_CLUSTER_GIC_LP_EB);
	CHIP_REG_OR(REG_AON_APB_APCPU_CLUSTER_SCU_LPC_CTRL, BIT_AON_APB_APCPU_CLUSTER_SCU_LP_EB);
	CHIP_REG_OR(REG_AON_APB_APCPU_DEBUG_PWR_LP_CTRL, BIT_AON_APB_APCPU_LP_EB_DEBUG_PWR);
	CHIP_REG_OR(REG_AON_APB_APCPU_GIC_COL_LP_CTRL, BIT_AON_APB_APCPU_LP_EB_GIC_COL);
	CHIP_REG_OR(REG_AON_APB_APCPU_GIC600_GIC_LPC_CTRL, BIT_AON_APB_APCPU_GIC600_GIC_LP_EB);
	CHIP_REG_OR(REG_AON_APB_APCPU_DDR_AB_LPC_CTRL, BIT_AON_APB_APCPU_DDR_AB_LP_EB);
	//In WhaleK, Ken recommends not enabled the bit
	//CHIP_REG_OR(REG_AON_APB_APCPU_DBG_BLK_LPC_CTRL, BIT_AON_APB_APCPU_DBG_BLK_LP_EB);
	CHIP_REG_OR(REG_AON_APB_APCPU_TOP_MTX_M0_LPC_CTRL,
		BIT_AON_APB_APCPU_TOP_MTX_MIAN_LP_EB|
		BIT_AON_APB_APCPU_TOP_MTX_S3_LP_EB |
		BIT_AON_APB_APCPU_TOP_MTX_S2_LP_EB |
		BIT_AON_APB_APCPU_TOP_MTX_S1_LP_EB |
		BIT_AON_APB_APCPU_TOP_MTX_S0_LP_EB |
		BIT_AON_APB_APCPU_TOP_MTX_M3_LP_EB |
		BIT_AON_APB_APCPU_TOP_MTX_M2_LP_EB |
		BIT_AON_APB_APCPU_TOP_MTX_M1_LP_EB |
		BIT_AON_APB_APCPU_TOP_MTX_M0_LP_EB
	);

	CHIP_REG_OR(REG_AON_APB_AON_MTX_MAIN_LPC_CTRL, BIT_AON_APB_AON_MTX_MAIN_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_M0_LPC_CTRL, BIT_AON_APB_AON_MTX_M0_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_M1_LPC_CTRL, BIT_AON_APB_AON_MTX_M1_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_M2_LPC_CTRL, BIT_AON_APB_AON_MTX_M2_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_M3_LPC_CTRL, BIT_AON_APB_AON_MTX_M3_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_M4_LPC_CTRL, BIT_AON_APB_AON_MTX_M4_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_M5_LPC_CTRL, BIT_AON_APB_AON_MTX_M5_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_M6_LPC_CTRL, BIT_AON_APB_AON_MTX_M6_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_S0_LPC_CTRL, BIT_AON_APB_AON_MTX_S0_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_S1_LPC_CTRL, BIT_AON_APB_AON_MTX_S1_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_S2_LPC_CTRL, BIT_AON_APB_AON_MTX_S2_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_S3_LPC_CTRL, BIT_AON_APB_AON_MTX_S3_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_S4_LPC_CTRL, BIT_AON_APB_AON_MTX_S4_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_S5_LPC_CTRL, BIT_AON_APB_AON_MTX_S5_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_S6_LPC_CTRL, BIT_AON_APB_AON_MTX_S6_LP_EB);
	CHIP_REG_OR(REG_AON_APB_AON_MTX_S7_LPC_CTRL, BIT_AON_APB_AON_MTX_S7_LP_EB);
	CHIP_REG_OR(REG_AON_APB_EAXI_MTX_M0_LPC_CTRL, BIT_AON_APB_EAXI_MTX_M0_LP_EB);
	CHIP_REG_OR(REG_AON_APB_EAXI_MTX_M1_LPC_CTRL, BIT_AON_APB_EAXI_MTX_M1_LP_EB);
	CHIP_REG_OR(REG_AON_APB_EAXI_MTX_M2_LPC_CTRL, BIT_AON_APB_EAXI_MTX_M2_LP_EB);
	CHIP_REG_OR(REG_AON_APB_EAXI_MTX_S0_LPC_CTRL, BIT_AON_APB_EAXI_MTX_S0_LP_EB);
	CHIP_REG_OR(REG_AON_APB_EAXI_MTX_S1_LPC_CTRL, BIT_AON_APB_EAXI_MTX_S1_LP_EB);
	CHIP_REG_OR(REG_AON_APB_EAXI_MTX_MAIN_LPC_CTRL, BIT_AON_APB_EAXI_MTX_MAIN_LP_EB);
}

void ap_lpc_config(void)
{
	CHIP_REG_OR(REG_AP_AHB_CLOCK_FREQUENCY_DOWN,
		BIT_AP_AHB_APB2APB_SCLK_AUTO_GATE_EN|
		BIT_AP_AHB_APB2APB_MCLK_AUTO_GATE_EN|
		BIT_AP_AHB_CGM_CLK_AON_AXI_AUTO_GATE_EN|
		BIT_AP_AHB_CGM_CLK_APCPU_AXI_AUTO_GATE_EN
	);
	CHIP_REG_OR(REG_AP_AHB_APB_PCLK_AUTO_GATE_EB,
		BIT_AP_AHB_SDIO_MST_PCLK_AUTO_GATE_EB|
		BIT_AP_AHB_EMMC_PCLK_AUTO_GATE_EB
	);

	CHIP_REG_OR(REG_AP_AHB_MMTX_M0_LPC, BIT_AP_AHB_MMTX_M0_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_M1_LPC, BIT_AP_AHB_MMTX_M1_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_M2_LPC, BIT_AP_AHB_MMTX_M2_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_M3_LPC, BIT_AP_AHB_MMTX_M3_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_M4_LPC, BIT_AP_AHB_MMTX_M4_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_M5_LPC, BIT_AP_AHB_MMTX_M5_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_M6_LPC, BIT_AP_AHB_MMTX_M6_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_MAIN_LPC, BIT_AP_AHB_CGM_MMTX_AUTO_GATE_EN | BIT_AP_AHB_MMTX_MAIN_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_S0_LPC, BIT_AP_AHB_CGM_MMTX_S0_AUTO_GATE_EN | BIT_AP_AHB_MMTX_S0_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_S1_LPC, BIT_AP_AHB_CGM_MMTX_S1_AUTO_GATE_EN | BIT_AP_AHB_MMTX_S1_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_S2_LPC, BIT_AP_AHB_CGM_MMTX_S2_AUTO_GATE_EN | BIT_AP_AHB_MMTX_S2_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_S3_LPC, BIT_AP_AHB_CGM_MMTX_S3_AUTO_GATE_EN | BIT_AP_AHB_MMTX_S3_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_S4_LPC, BIT_AP_AHB_CGM_MMTX_S4_AUTO_GATE_EN | BIT_AP_AHB_MMTX_S4_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_S5_LPC, BIT_AP_AHB_CGM_MMTX_S5_AUTO_GATE_EN | BIT_AP_AHB_MMTX_S5_LP_EB);
	CHIP_REG_OR(REG_AP_AHB_MMTX_S6_LPC, BIT_AP_AHB_CGM_MMTX_S6_AUTO_GATE_EN | BIT_AP_AHB_MMTX_S6_LP_EB);

	CHIP_REG_OR(REG_AP_IPA_AHB_APB_PCLK_AUTO_GATE_EB,
		BIT_AP_IPA_AHB_SDIO_SLV_PCLK_AUTO_GATE_EB |
		BIT_AP_IPA_AHB_PCIE_SNPS_PCLK_AUTO_GATE_EB |
		BIT_AP_IPA_AHB_PCIE_XZ_PCLK_AUTO_GATE_EB |
		BIT_AP_IPA_AHB_USB_PAM_PCLK_AUTO_GATE_EB
	);

	CHIP_REG_OR(REG_AP_IPA_AHB_AP_SYS_FORCE_SLEEP_CFG, BIT_AP_IPA_AHB_CGM_CLK_AP_AXI_AUTO_GATE_EN);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M0_LPC, BIT_AP_IPA_AHB_IMTX_M0_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M1_LPC, BIT_AP_IPA_AHB_IMTX_M1_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M2_LPC, BIT_AP_IPA_AHB_IMTX_M2_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M3_LPC, BIT_AP_IPA_AHB_IMTX_M3_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M4_LPC, BIT_AP_IPA_AHB_IMTX_M4_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M5_LPC, BIT_AP_IPA_AHB_IMTX_M5_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M6_LPC, BIT_AP_IPA_AHB_IMTX_M6_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M7_LPC, BIT_AP_IPA_AHB_IMTX_M7_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M8_LPC, BIT_AP_IPA_AHB_IMTX_M8_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M9_LPC, BIT_AP_IPA_AHB_IMTX_M9_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_M10_CTRL, BIT_AP_IPA_AHB_IMTX_M10_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_MAIN_LPC, BIT_AP_IPA_AHB_CGM_IMTX_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_MAIN_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S0_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S0_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S0_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S1_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S1_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S1_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S2_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S2_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S2_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S3_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S3_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S3_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S4_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S4_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S4_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S5_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S5_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S5_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S6_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S6_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S6_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S7_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S7_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S7_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S8_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S8_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S8_LP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_IMTX_S9_LPC, BIT_AP_IPA_AHB_CGM_IMTX_S9_AUTO_GATE_EN | BIT_AP_IPA_AHB_IMTX_S9_LP_EB);

	CHIP_REG_OR(REG_AP_IPA_AHB_IPA_CTRL, BIT_AP_IPA_AHB_IPA_DFS_VOTE_LSLP_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_PAM_WIFI_PCLK_DFS_CTRL, BIT_AP_IPA_AHB_PAM_WIFI_PCLK_AUTO_GATE_EB);
	CHIP_REG_OR(REG_AP_IPA_AHB_CGM_GATE_EN,
		BIT_AP_IPA_AHB_CGM_CLK_CP1_AXI_AUTO_GATE_EN |
		BIT_AP_IPA_AHB_CGM_CLK_CP0_AXI_AUTO_GATE_EN
	);
}

// Clock auto gate
void clock_auto_gate(void)
{
	uint32_t value = 0U;

	value = CHIP_REG_GET(REG_AON_APB_RC100M_CFG) & ~BIT_AON_APB_RC100M_FORCE_EN | BIT_AON_APB_RC100M_AUTO_GATE_EN;
	CHIP_REG_SET(REG_AON_APB_RC100M_CFG, value);

	CHIP_REG_OR(REG_AON_APB_AUTO_GATE_CTRL0, BIT_AON_APB_CGM_AP_AXI_APCPU_AUTO_GATE_SEL);

	value = CHIP_REG_GET(REG_AON_APB_AUTO_GATE_CTRL0) & ~BIT_AON_APB_CGM_AP_AXI_FORCE_EN | BIT_AON_APB_CGM_AP_AXI_AUTO_GATE_SEL;
	CHIP_REG_SET(REG_AON_APB_AUTO_GATE_CTRL0, value);

	value = CHIP_REG_GET(REG_AON_APB_AUTO_GATE_CTRL0) & ~BIT_AON_APB_CGM_APCPU_PMU_FORCE_EN | BIT_AON_APB_CGM_APCPU_PMU_AUTO_GATE_SEL;
	CHIP_REG_SET(REG_AON_APB_AUTO_GATE_CTRL0, value);

	value = CHIP_REG_GET(REG_AON_APB_AUTO_GATE_CTRL1) & ~BIT_AON_APB_CGM_TOP_DVFS_ROOT_FORCE_EN | BIT_AON_APB_CGM_TOP_DVFS_ROOT_AUTO_GATE_SEL;
	CHIP_REG_SET(REG_AON_APB_AUTO_GATE_CTRL1, value);

	CHIP_REG_OR(REG_AON_APB_AUTO_GATE_CTRL3,
		BIT_AON_APB_CGM_PERIPH_AUTO_GATE_EN |
		BIT_AON_APB_CGM_GIC_AUTO_GATE_EN |
		BIT_AON_APB_CGM_ACP_AUTO_GATE_EN |
		BIT_AON_APB_CGM_AXI_PERIPH_AUTO_GATE_EN |
		BIT_AON_APB_CGM_ACE_AUTO_GATE_EN |
		BIT_AON_APB_CGM_SCU_AUTO_GATE_EN |
		BIT_AON_APB_CGM_CORE1_AUTO_GATE_EN |
		BIT_AON_APB_CGM_CORE0_AUTO_GATE_EN
	);

	/*value = CHIP_REG_GET(REG_TOP_DVFS_APB_TOP_DVFS_CLK_CTRL) & ~BIT_TOP_DVFS_APB_CGM_TOP_DVFS_FORCE_EN | BIT_TOP_DVFS_APB_CGM_TOP_DVFS_AUTO_GATE_SEL;
	CHIP_REG_SET(REG_TOP_DVFS_APB_TOP_DVFS_CLK_CTRL, value);

	value = CHIP_REG_GET(REG_APCPU_DVFS_APB_CGM_APCPU_DVFS_CLK_GATE_CTRL) & ~BIT_APCPU_DVFS_APB_CGM_APCPU_DVFS_FORCE_EN | BIT_APCPU_DVFS_APB_CGM_APCPU_DVFS_AUTO_GATE_SEL;
	CHIP_REG_SET(REG_APCPU_DVFS_APB_CGM_APCPU_DVFS_CLK_GATE_CTRL, value);

	value = CHIP_REG_GET(REG_AP_DVFS_APB_CGM_AP_DVFS_CLK_GATE_CTRL) & ~BIT_AP_DVFS_APB_CGM_AP_DVFS_FORCE_EN | BIT_AP_DVFS_APB_CGM_AP_DVFS_AUTO_GATE_SEL;
	CHIP_REG_SET(REG_AP_DVFS_APB_CGM_AP_DVFS_CLK_GATE_CTRL, value);*/
}

void CSP_Init(uint32_t gen_para)
{
	pmu_commom_config();
	apcpu_hw_dvfs_config();
	pad_out_sel_config();
	aon_idle_config();
	aon_lpc_config();
	ap_lpc_config();
	clock_auto_gate();
}

/**---------------------------------------------------------------------------*
 **                         Compiler Flag                                     *
 **---------------------------------------------------------------------------*/
#ifdef __cplusplus
}
#endif


